Tuesday, 31 May 2011

Video - Update 2

A little more progress made.  I have routed the R2R DACs and HSYNC and VSYNC signals to a 4x2 pin header.  This will go out to a chassis mounted VGA port.

I think I have mostly worked out how I'll coordinate between the two GPU.  I have introduced a D-Type Flip-flop to perform the role of a hardware mutex.  When the GPU AVRs start up, they will read the value on their PORTD5 pin.  The left hand GPU PORTD5 pin will be connected to the Q output of the Flip Flop and PORTD5 on the other GPU will be connected to Q'.  Whichever GPU reads a high value is going to render while the other will perform the RAMDAC role.  Then the Flip-flop flips, the roles will reverse. 

The RAMDAC GPU will be responsible for handing off to the other.  The hand off process will look like this:
  1. At the end of the video frame the RAMDAC GPU will drive the Flip-flop clock pin high causing:
    1. The Flip-flop will toggle.
    2. The VSYNC will go high (or high depending on how I wire it)
    3. The Serial ports will be connected to the new Render GPU.
    4. The SRAM data line buffers will toggle their enabled state.
    5. The SRAM address line buffers will toggle their enabled state.
  2. The new RAMDAC will wait for the VSYNC period and then drive the Flip-flop clock pin low.
  3. The new Render GPU will set appropriate pins to High-Z and then can get on with rendering.

Things left to do on the video board:
  • Ground plane
  • Decoupling capacitors